The SST49LF040 flash memory devices can operate in
two distinct interface modes: the LPC mode and the Paral-
lel Programming (PP) mode. The mode pin is used to set
the interface mode selection. If the mode pin is set to logic
High, the device is in PP mode; while if the mode pin is set
Low, the device is in the LPC mode. The mode selection
pin must be configured prior to device operation. The mode
pin is internally pulled down if the pin is left unconnected. In
LPC mode, the device is configured to its host using stan-
dard LPC interface protocol. Communication between Host
and the SST49LF040 occurs via the 4-bit I/O communica-
tion signals, LAD [3:0] and LFRAME#. In PP mode, the
device is programmed via an 11-bit address and an 8-bit
data I/O parallel signals. The address inputs are multi-
plexed in row and column selected by control signal R/C#
pin. The row addresses are mapped to the higher internal
addresses, and the column addresses are mapped to the
lower internal addresses. See Figure 1, the Device Mem-
ory Map, for address assignments.
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